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device operating temperature range package semiconductor technical data chroma 4 video processor ordering information mc44002p t a = 0 to +70 c plastic dip p suffix plastic package case 711 40 1 pin connections order this document by mc44002/d 38 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 (top view) acc video 2 i ref clock data v-ramp v-drive e-w drive osc loop filter ident r-y b-y v cc gnd (17.7 mhz) i anode analog contrast secam cal loop h-drive h-flyback input 2 1 (14.3 mhz) sandcastle system select y1 output y1 clamp r-y b-y signal gnd r g b feedback y2 r g b fast commutate outputs h-loop filter inputs inputs crystals outputs video 1 in i 2 c MC44007p plastic dip 1 motorola analog ic device data

the mc44002/7 is a highly advanced circuit which performs most of the basic functions required for a color tv. all of its advanced features are under processor control via an i 2 c bus, enabling potentiometer controls to be removed completely. in this way the component count may be reduced dramatically, allowing significant cost savings together with the possibility of implementing sophisticated automatic test routines. using the mc44002/7, tv manufacturers will be able to build a standard chassis for anywhere in the world. additional features include 4 selectable matrix modes (primarily for ntsc), fast beam current limiting and 16:9 display. ? operation from a single 5.0 v supply; typical current consumption only 120 ma ? full pal/secam/ntsc capability (4 matrix modes) ? dual composite video or s-vhs inputs ? all chroma/luma channel filtering, and luma delay line are integrated using sampled data filters requiring no external components ? filters automatically commutate with change of standard ? chroma delay line is realized with a 16 pin companion device, the mc44140 ? rgb drives incorporate contrast and brightness controls and auto gray scale ? switched rgb inputs with separate saturation control ? auxiliary y, r-y, b-y inputs ? line timebase featuring h-phase control, time constant and switchable phase detector gain ? vertical timebase incorporating vertical geometry corrections ? 16:9 display mode capability ? e-w parabola drive incorporating horizontal geometry corrections ? beam current monitor with breathing compensation ? analog contrast control, allowing fast beam current limitation ? MC44007 decoders pal/ntsc only maximum ratings (t a = 25 c, unless otherwise noted.) rating pin symbol value unit supply voltage 35 v cc 6.0 vdc operating ambient temperature t a 0 to + 70 c storage temperature t stg 65 to +150 c junction temperature t j +150 c drive output sink current 12 i 12 2.0 ma applied voltage range: vdc feedback 20 v 20 0 to +8.0 anode current 9 v 9 2.0 to v cc all other pins v i 0 to v cc esd v note: esd data available upon request. this document contains information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 1996 rev 1
mc44002 MC44007 2 motorola analog ic device data maximum ratings (t a = 25 c, unless otherwise noted.) rating unit value symbol pin human body model 2000 machine model 200 note: esd data available upon request. chroma takeoff filter matrix switching & rgb sat control luma select 17.7 mhz video 1 (s-vhs) video 2 y2 r-y b-y fast comm. filter filter system select sat & hue system r-y b-y y1 memory/control registers y1 clamp parab gen beam current monitor control loops rx/tx red green blue red green blue rgb outputs analog contrast fdbck data clk anode current e-w drive freq divider flyback sense 14.3 mhz loop 2 h flyback pulse h drive 5.0 v v drive 5.0 v i ref v sync pal/ ntsc/ secam decoder ident clk vert sync sep osc pll 1 ramp gen luma delay peaking & trap acc sand- castle sync sep input select 240 31 130 38 37 36 29 14 15 39 32 33 25 27 26 28 21 24 22 17 18 19 16 10 20 5 4 9 8 6 3 7 13 12 35 34 23 simplified block diagram 11 i 2 c bus this device contains 6,245 active transistors. electrical characteristics (v cc = 5.0 vdc, i 3 = 70 m a, t a = 25 c, unless otherwise noted.) characteristic pin min typ max unit supply voltage 35 4.75 5.0 5.25 v operating current 35 90 120 180 ma reference current, input voltage 3 1.0 1.3 1.6 v thermal resistance, junctiontoambient 56 c/w notes: composite video input signal level = 1.0 vpp horizontal timebase started (subaddress 00) black-to-white = 0.vpp7 , syn-to-black = 0.3 vpp vertical breathing control set to 00; v9 = 0 v pal/ntsc = 75% color bars; burst = 300 mvpp all other analog controls set to midrange 32 secam = 75% color bars video peaking ap1, p2, p3o bits high
mc44002 MC44007 3 motorola analog ic device data test conditions (unless otherwise noted.) v cc = 5.0 v i ref = 70 m a t a = 25 c video composite input = 1.0 vpp blacktowhite = 0.7 vpp blacktosync = 0.3 vpp horizontal timebase started (reg. 00) vertical breathing control set to 00 pin 9 = 0 v pin 10 = 5.0 v pal/ntsc = 75% color bars burst = 300 mvpp secam = 75% color bars (mc44002 only) all analog controls set to midpoint (32) luma peaking at min. (p1 p3 = 111) control bits setup name value function status v1/v2 1 video input 1 selected h en 0 horizontal drive enabled bri en 1 abrighto sample aono hgain1 0 horizontal phase detector gain reduced by 3 enabled yx en 0 luma matrix disabled y1 en 1 luma from filters aono d en 0 rgb inputs enabled xs 0 pin 33 crystal enabled test 1 outputs sampled once/field fsi 0 50 hz field rate t3 1 low pass filter enabled vd1 1 4:3 display mode 2xfh 0 horizontal drive at 1xfh norm 0 horizontal reference divider for 17.7 mhz hgain2 1 horizontal phase detector gain reduced by 2 enabled intsel 1 long vertical time constant y2 en 0 external luma input aoffo ssd 0 secam mode select enabled calkil 1 horizontal calibration loop enabled bai 1 vertical blanking for 625 lines svhs 1 composite video input
mc44002 MC44007 4 motorola analog ic device data electrical characteristics parameter symbol pin min typ max unit bus requirements maximum output low voltage v ol(max) 5 0.7 v i sink = 1.0 ma, device in areado mode maximum sink current i sink(max) 5 1.0 ma v ol = 0.7 v, device in areado mode minimum input high voltage v ih(min) 5 3.0 v maximum input low voltage v il(max) 5 1.5 v maximum rise time t r(max) 4, 5 1.0 m s between v ih and v il levels scl clock frequency f scl 4 100 khz horizontal timebase freerunning frequency (calibration mode) 31 khz 17.734475 mhz crystal. anormo bit = 0; ah eno bit = 1 (horizontal drive disabled) 15.39 15.625 15.85 14.31818 mhz crystal. anormo bit = 1; ah eno bit = 1 (horizontal drive disabled) 15.42 15.75 15.98 hloop 1 (pin 15 current forced to 20 m a) 12 khz minimum frequency 13.85 14.25 14.65 maximum frequency 16.05 16.55 17.05 frequency range 2.3 vco control gain 12, 15 1.9 2.4 2.9 khz/v phase detector gain 15 18 27 39 m a/ m s ahgain1 o bit = 1; ahgain2o bit = 0 phase detector gain reduction factor 15 ahgain1 a bit switched from 1 to 0 2.5 3.0 3.5 ahgain2a bit switched from 0 to 1 1.75 2.0 2.25 line drive output saturation voltage 12 0.25 0.5 v i12 = 1.0 ma horizontal drive pulse low 12 27 m s defined by internal counter, deflection transistor aoffo, period is 64 m s horizontal flyback input resistance 13 50 k w v13 = 2.0 v horizontal flyback clamping voltages 13 v i13 = 500 m a 5.7 i13 = 50 m a 0.5 horizontal flyback threshold current 13 30 m a should be externally limited to 500 m a peak by an external resistor horizontal phase control range 12 8.0 12 m s flyback duration: 12 m s external delay compensation 12, 13 6.0 18 m s from horizontal drive to center of flyback pulse. flyback duration: 12 m s vertical timebase (all values are related to pin 3 reference current) vertical drive amplitude (4:3 display) 7 v (00) 1.15 1.33 1.5 (32) 1.55 1.75 1.95 (63) 1.95 2.18 2.4 c6 = 82 nf, assuming zero tolerance capacitance, avdio set to a1o vertical drive amplitude control range (4:3 display) 7 0.75 0.85 1.0 v c6 = 82 nf, assuming zero tolerance capacitance, avdio set to a1o, vertical amplitude varied from (00) to (63)
mc44002 MC44007 5 motorola analog ic device data electrical characteristics (continued) parameter unit max typ min pin symbol vertical timebase (all values are related to pin 3 reference current) ramp amplitude ratio between 4:3 and 16:9 display modes 7 0.7 0.8 0.9 vertical amplitude = (32) maximum ramp amplitude change with 525/625 mode change 7 2.0 % vertical ramp low voltage (4:3 display) 7 0.65 v pin 6 voltage set to 0 v, avdio set to a1o, vertical position = (00) vertical ramp low voltage (16:9 display) 7 0.85 v pin 6 voltage set to 0 v, avdio set to a0o, vertical position = (00), measured after 16:9 holding period vertical ramp high voltage 7 4.15 v pin 6 open, avdio set to a0o or a1o, vertical position = (63) vertical ramp position control range 7 0.5 0.75 1.0 v versus vertical ramp voltage at vertical position (32), measured at v m , avdio set to a0o or a1o, vertical position varied from (00) to (63) vertical ramp clamping duration (t c ) 7 512 m s defined by internal counter maximum output source current 7 1.0 ma maximum output sink current 7 200 m a vertical linearity 7 (00) 0.8 (63) 1.1 change in ramp current as pin 9 current varied from 0 to 6.4 m a 6 m a vertical breathing correction = (63) 0.15 0.75 1.3 vertical breathing correction = (00) 0 gain v7/v6 6, 7 0.9 0.95 1.0 v/v ew correction (v6(b) = 0.2 v, v6(m) = 1.1 v, v6(e) = 2.0 v) horizontal amplitude 8 m a (00) 0 0.2 20 (63) 150 300 corner correction = (00), tilt = (32), parabola amplitude = (00), measured at t m . parabola amplitude 8 m a (00) 0 0.2 10 (63) 100 250 corner correction = (00), horizontal amplitude = (32), tilt = (32), measured at t b , t m and t e. corner correction 8 m a (00) 0 0.2 10 (63) 150 30 horizontal amplitude = (63), parabola amplitude = (00), tilt = (32), measured at t b , t m and t e . parabola tilt 8 (00) 1.9 (63) 1.9 corner correction = (00), horizontal amplitude = (32), parabola amplitude = (32), measured at t b , t m and t e . ew drive output voltage 8 1.0 v cc v
mc44002 MC44007 6 motorola analog ic device data electrical characteristics (continued) parameter unit max typ min pin symbol ew correction (v6(b) = 0.2 v, v6(m) = 1.1 v, v6(e) = 2.0 v) ew dacs differential nonlinearity error 8 lsb at minor transitions: steps 01: 12; 34; 78; 1516. 1.0 1.0 at major transition: step 3132 2.0 1.0 sync separator sync amplitude to operate the device 2, 40 100 mv from black to sync, black picture, standard timing specifications on sync signal 22, 23, 24, 25 160 vertical sync separator delay time: t d 2, 40 m s aintselo = 0 36 aintselo = 1 68 from vertical sync pulse to vertical ramp reset vertical sync window 2, 40, 22, 23, 24, 25 448 740 half lines composite video processing (all measurements in normal mode, unless otherwise noted.) composite video input amplitude 2, 40 0.7 1.0 1.4 vpp load impedance 75 w , less than 5% distortion video 1/video 2 input crosstalk 29 40 db @ f = (2.0 mhz), measured on y1 output variable input lpf cutoff frequency 29 mhz 17.7 mhz crystal selected 6.0 14.3 mhz crystal selected 4.85 chroma subcarrier rejection 29 db pal 4.43 mhz (17.7 mhz crystal selected) 25 30 ntsc 3.58 mhz (14.3 mhz crystal selected) 25 30 secam (f o r and f o b) (17.7 mhz crystal selected) 18 20 y1 output resistance 29 300 w y1 bandwidth (3.0 db) 29 mhz pal minimum peaking, at3o set to 1 (input lpf aono) 2.5 3.0 secam minimum peaking, at3o set to 0 (input lpf aoffo) 2.5 3.0 luma peaking range 29 6.0 8.5 db measured at 3.0 mhz, 17.7 mhz crystal selected luma gain (@ 100 khz) 2, 40, 29 0.9 1.1 1.3 v/v overshoot 29 5.0 % peaking at step 3 (100) source impedance 2, 40 0 1.5 k w luma delay range 29 ns pal/secam (17.7 mhz crystal selected) 280 ntsc 3.58 (14.3 mhz crystal selected) 350 video in to luma out delay difference between pal and secam (mc44002 only) 29, 40 260 ns luma delay minimum: (d1 d2 d3) = (0 0 0), green to magenta transition, at3o set to 1 in pal, to 0 in secam pal/ntsc decoder chroma output variation 36, 37 3.0 db for a burst input varied from 60 mv to 600 mv color kill attenuation 36, 37 40 db referred to standard color video input, monochrome mode selected
mc44002 MC44007 7 motorola analog ic device data electrical characteristics (continued) parameter unit max typ min pin symbol pal/ntsc decoder color difference output distortion 36, 37 5.0 % @ 1.5 v output signal residual chroma subcarrier rejection 36, 37 db pal 40 ntsc 40 referred to video input oscillator pullin range 32, 33 hz pal 350 ntsc 400 referred to nominal subcarrier frequency, with ideal xtal ry, by channel separation 36, 37 30 db by/ry amplitude ratio 36, 37 1.3 v/v at standard color bars signal by/ry amplitude ratio spread 36, 37 2.0 2.0 db at standard color bars signal minimum burst level for aacc activeo flag aono 2, 40 10 20 mvpp standard set to pal or ntsc, increasing burst level steps minimum burst level for apal identifiedo flag aono 2, 40 5.0 20 mvpp standard set to pal or ntsc, increasing burst level steps maximum burst level for aacc activeo flag aoffo 2, 40 5.0 mvpp standard set to pal or ntsc, decreasing burst level steps maximum burst level for apal identifiedo flag aoffo 2, 40 1.0 mvpp standard set to pal or ntsc, decreasing burst level steps (by) color difference output levels 36 0.7 1.1 1.5 v relative to 75% color bars hue dac control range 36, 37 20 deg hue control register varying from (00) to (63) chroma to luma delay 29, 36 ns pal 80 ntsc 100 measured on (by) output, luma delay set to minimum: (d1 d2 d3) = (0 0 0), green to magenta transition, at3o set to 1 delay line control signals system select 30 pal 75 400 mv ntsc 1.4 1.65 1.9 v secam (mc44002 only) 2.75 3.0 3.25 v external 3.7 4.0 4.3 v sandcastle 31 level 1 3.7 4.0 4.3 v level 2 2.75 2.95 3.15 v level 3 1..3 1.55 1.8 v level 4 75 mv see figure 4 sandcastle 31 m s t1 5.0 6.0 7.0 t2 4.0 5.0 6.0 see figure 4, values defined by internal counter
mc44002 MC44007 8 motorola analog ic device data electrical characteristics (continued) parameter unit max typ min pin symbol svhs video processing (svhs set to 0, at3o set to 0) y1 bandwidth 29 3.2 3.5 mhz luma peaking set to minimum minimum burst level for aacc activeo flag aono 2, 40 10 20 mvpp standard set to pal or ntsc, increasing burst level steps minimum burst level for apal identifiedo flag aono 2, 40 5.0 20 mvpp standard set to pal or ntsc, increasing burst level steps maximum burst level for aacc activeo flag aoffo 2, 40 5.0 mvpp standard set to pal or ntsc, decreasing burst level steps maximum burst level for apal identifiedo flag aoffo 2, 40 1.0 mvpp standard set to pal or ntsc, decreasing burst level steps video in to luma out delay difference between svhs and normal mode 2, 40, 29 310 ns luma delay minimum in normal mode, set to step 6 in svhs mode, green to magenta transition, at3o set to 1 in normal mode, to 0 in svhs mode chroma to luma delay difference between svhs and normal mode 29, 36, 2, 40 60 ns measured on (by) output, luma delay minimum in normal mode, set to step 6 in svhs mode, green to magenta transition, at3o set to 1 in normal mode, to 0 in svhs mode secam decoder (mc44002 only) minimum subcarrier level for asecam identifiedo flag 2, 40 10 20 mvpp measured at f o r color kill attenuation 36, 37 40 50 db monochrome mode selected referred to color difference output signal with secam selected and identified color difference zero level error 36, 37 1.0 3.0 % relative to 75% color bars, difference between signal measured at t1 and active black level (black bar) color difference output distortion 36, 37 5.0 % subcarrier level at f o r = 20400 mv @ 1.5 v output signal transient response ns (by) 36 650 800 (ry) 37 750 900 generator rise time 600 ns (by), green to magenta transition, measured between 10% and 90% levels by/ry amplitude 36, 37 ratio 1.3 v/v ratio spread 2.0 2.0 db relative to 75% color bars residual carrier and harmonics (4.0 to 13.5 mhz) 36, 37 1.0 % at standard color bars signal (by) color difference output levels 36 1.1 v relative to 75% color bars pal/secam color difference ratio 36 0.8 1.0 1.2 nominal input signals
mc44002 MC44007 9 motorola analog ic device data electrical characteristics (continued) parameter unit max typ min pin symbol secam decoder (mc44002 only) chroma to luma delay 29, 36 420 ns luma delay set to minimum: (d1 d2 d3) = (0 0 0), green to magenta transition, at3o set to 0 patterning 36 5.0 % full screen 75% color frequency, 500 khz low pass filter, relative to black to color output signal line to line luma levels difference 29 1.5 % full screen 75% yellow color frequency, relative to black to yellow output signal chroma to luma delay difference between pal and secam 29, 36 340 ns measured on (by) output, luma delay set to minimum: (d1 d2 d3) = (0 0 0), green to magenta transition, at3o set to 0 in secam, to 1 in pal color difference stages rgb input amplitude 22, 23, 500 700 1000 mvpp black to peak (less than 5% distortion at rgb outputs) 24 fast commutate 21 v low level 0.5 high level 1.0 y2 input amplitude 25 0.7 1.0 1.4 vpp (less than 5% distortion at rgb outputs) color difference input amplitude 26, 27 1.8 vpp (less than 5% distortion at rgb outputs) y2/y1 crosstalk 25, 29 40 30 db measured at rgb outputs, measured at f = (2.0 mhz) rgb to y crosstalk 22, 23, 40 30 db measured at rgb outputs, measured at f = (2.0 mhz) 24, 25, 29 rgb transconductance bandwidth (@ 1.0 db) 24, 17, 23, 18, 22, 19 6.5 mhz gain reduction in acl mode 10, 17, 12.5 db pin 10 voltage varying from 0 to 5.0 v 18, 19 gain reduction sensitivity in acl mode 10, 17, 20 db/v pin 10 voltage varying from 2.0 to 2.5 v 18, 19 demodulation angles and amplitudes deg mode a rm 0.562 ra 90 gm 0.344 ga 237 mode b rm 0.9 ra 100 gm 0.3 ga 236 mode c rm 0.9 ra 106 gm 0.3 ga 240 mode d rm 0.91 ra 106 gm 0.31 ga 246 definitions: rm/gm = module, ra/ga = argument
mc44002 MC44007 10 motorola analog ic device data electrical characteristics (continued) parameter unit max typ min pin symbol rgb output stages low dark sample output current 17, 18, ma red 19 3.15 green 3.15 blue 3.15 dark sample cathode current 5.0 to 15 m a, dc dac set to full scale, see figure 1 high dark sample output current 17, 18, ma red 19 3.95 green 3.95 blue 3.95 dark sample cathode current 5.0 to 15 m a, dc dac set to zero, see figure 1 blanking output current 17, 18, 19 6.0 ma maximum y to rgb output transconductance 17, 18, 6.0 7.0 8.0 ma/v gain dac set to full scale 19 brightness v (00) 30 (63) 20 wrt dark sample cathode voltage, high voltage output stage transimpedance 39 k w , dark sample cathode current 15 m a, dark sample cathode voltage 140 v rgb dark sample current intensity range 20 15 20 db rgb intensity dacs varying from (00) to (63) bright to dark sample current ratio 20 8.0 9.5 11 m a/ m a leakage loop 20 m a sink current 20 source current 5.0 average beam current detection level 9 v excess flag 0.9 1.0 1.1 overload flag 1.3 1.2 1.1 peak beam current detection level 20 6.5 6.8 7.1 v figure 1. example of output circuitry v p , v ref , r fdbk and r p values will determine the exact operating point. for example, let us take: v p = 5.0 v r fdbk = 39 k w v ref = 3.6 v r p = 6.8 k w the formula giving the dark cathode voltage with above circuit is: v dk = v ref + r fdbk *(v ref v p + lodk*r p ) / r p with above application, component values and lodk specifications, all 3 cathodes on all devices will always have a range of at least 120 v to 150 v. by changing the values of v p , v ref and r p , the cathode voltage range may be shifted up or down as required. lodk v ref v dk picture tube cathode r fdbk r p v p pins 17, 18, 19 mc44002/7p
mc44002 MC44007 11 motorola analog ic device data figure 2. vertical waveforms figure 3. vertical ramp positions (v7 versus v6) 1.6 ms 18.4 ms t b t m t e v b v m v e i b i m i e t d t c video signal vertical ramp waveform parabola waveform v ramp high voltage v ramp low voltage (xx) = values of (80) register (63) pin 6 voltage (v) pin 7 voltage (v) 4 1 (32) (00) 3 2 1 23 4
mc44002 MC44007 12 motorola analog ic device data definitions parabola amplitude (i b i e ) 2 i m parabola tilt (i e i b ) parabola amplitude horizontal amplitude i m vertical amplitude v e v b vertical linearity (v e v m ) v m v b corner correction is calculated in the same way as parabola amplitude. figure 4. sandcastle output (pin 31) 64 m s 1 2 4 3 t1 t2 general description of the chroma 4 system figure 5 shows a simplified block diagram representation of the basic system using the mc44002/7 and its companion device the mc44140 chroma delay line. the mc44002/7 has been designed to carry out all the processing of video signals, display controls and timebase functions. there are two video inputs which can be used for normal composite video or separate y and c inputs. in either case, the inputs are interchangeable and selection is made via the i 2 c bus. the video is decoded within the mc44002/7 and involves separation, filtering, delay of the luminance part of the signal and demodulation of the chroma into color difference signals. the luminance (called y1) together with the demodulated r-y and b-y are all then brought out from the ic. the color difference signals then enter the mc44140 which performs color correction in pal and the delay line function in secam. corrected color difference signals then re-enter the mc44002/7.
mc44002 MC44007 13 motorola analog ic device data figure 5. connection to tv chassis b b g g r r g2 g1 eht v o/p stage v-scan coils 26 v line o/p stage e-w amplifier diode modulator linearity h-scan coils focus eht tripler 5.0 v line output transformer h-flyback h-drive anode current e-w drive v-drive analog contrast r-o/p g-o/p b-o/p feedback 0 v data clock 14.3 mhz 17.7 mhz fast commutate b in g in r in y2 in ext b-y ext r-y b-y in r-y in b-y out r-y out y1 out video 2 video 1 g3 i 2 c bus mc44002/7 mc44140 h.t. comp video or s-vhs beam current limitation 12 v the next stage is called the color difference stage where a number of control functions are carried out together with matrixing of the components to derive rgb signals. at this point a number of auxiliary signals may also be switched in, again all under mcu control. external rgb (text) and fast commutate enter here; also an external luminance (y2) may be used instead of y1. external r-y and b-y are switched in via the delay line circuit to save pins on the main device. the y2 and external r-y, b-y will obviously be of considerable benefit from the system point of view for use with external decoders. the final stage of video processing is the rgb outputs which drive the high voltage amplifiers connected to the tube cathodes. these outputs are controlled by a sophisticated digital servo-loop which is maintained and stabilized by a sequentially sampled beam current feedback system. automatic gray scale control is featured as a part of this system. both horizontal and vertical timebases are incorporated into the mc44002/7 and control is via the i 2 c bus. the horizontal timebase employs a dual loop system of a pll and variable phase shifter, and the vertical uses a countdown system. for the vertical, a field rate sawtooth is available which is used to drive an external power amplifier with flyback generator (usually a single ic). the line output consists of a pulse which drives a conventional line output stage in the normal way. the line flyback pulse is sensed and used by the second loop for horizontal phase shift. where e-w correction is required, a parabola waveform is available for this which, with the addition of a power amplifier, can be used with a diode modulator type line output stage for dynamic width and e-w control. the bottom of the eht overwinding is returned to the mc44002/7 and is used for anode current monitoring. fast beam current limitation is also made possible by the use of an analog contrast control. a much more detailed description of each stage of the mc44002/7 will be found in the next section. information on the delay line is to be found in its own data sheet.
mc44002 MC44007 14 motorola analog ic device data introduction the following information describes the basic operation of the mc44002/7 ic together with the mc44140 chroma delay line. the mc44002/7 is a highly advanced circuit which performs all the video processing, timebase and display functions needed for a modern color tv. the device employs analog circuitry but with the difference that all its advanced features are under processor control, enabling external filtering and potentiometer adjustments to be removed completely. sophisticated feedback control techniques have been used throughout the design to ensure stable operating conditions and the absence of drift with age. the ic described herein is one of a new generation of tv circuits, which make use of a serial data bus to carry out control functions. its revolutionary design concept permits a level of integration and degree of flexibility never achieved before. the mc44002/7 consists of a single bipolar vlsi chip which uses a high density, high frequency, low voltage process called mosaic 1.5. contained within this single 40 pin package is all the circuitry needed for the video signal processing, horizontal and vertical timebases and crt display control for today's color tv. furthermore, all the user controls and manufacturer's set-up adjustments are under the control of the processor i 2 c bus, eliminating the need for potentiometer controls. the mc44002/7 offers an enormous variety of different options configurable in software, to cater to virtually any video standard or circumstance commonly met. the decoder section offers full multistandard capability, able to handle pal, secam (mc44002 only) and ntsc standards with 4 matrix modes available. practically all the filtering is carried out onboard the ic by means of sampled data filters, and requires no external components or adjustment. digital interface one of the most important features of mc44002/7 is the use of processor control to replace external potentiometer and filter adjustments. great flexibility is possible using processor control, as each user can configure the software to suit their individual application. the circuit operates on a bidirectional serial data bus, based on the well known i 2 c bus. this system is rapidly becoming a world standard for the control of consumer equipment. i 2 c bus it is not within the scope of this data sheet to describe in detail the functioning of the i 2 c bus. basically, the i 2 c bus is a two-wire bidirectional system consisting of a clock and a serial data stream. the write cycle consists of 3 bytes of data and 3 acknowledge bits. the first byte is the chip address, the second the sub-address to identify the location in the memory, and the third byte is the data. when the address' read/write bit is high, the second and third bytes are used to transmit status flags back to the mcu. figure 6 shows a block diagram of the mc44002/7 bus interface/decoder. to begin with, the start bit is recognized by means of the data going low during clk high. this causes the counter and all the latches to be reset. for a write operation, the write address ($88) is read into the shift register. if the correct address is identified, the chip address latch is set and at clk 9 an acknowledge is sent. the second byte is now read into the shift register and is used to select the sub-address. at clk 18 a sub-address enable is sent to the memory to allow the data in the register to be changed. also, at clk 18 another acknowledge is sent. the third byte is now read into the shift register and the data bussed into the memory. the data in the sub-address location already selected is then altered. a third acknowledge is sent at clk 27 to complete the cycle. a read address ($89) indicates that the mcu wants to read the mc44002/7 status flags. in this instance, the read/write latch is set, causing the memory enable and subaddress enable to be inhibited, and the flags to be written onto the data line. two of the status flags are permanently wired one-high and one-low (o.k. and fault), to provide a check on the communication medium between the mc44002/7 and the mcu. at start-up the counter is automatically reset and the data for each sub-address is read in from the mcu. only after the entire memory contents have been transmitted, is data 00 sent to register 00 to start the horizontal drive. the mc44002/7 needs the full 27 clock cycles, or a stop condition, to properly release the i 2 c bus. 4 figure 6. i 2 c bus interface and decoder 8-bit shift register read/write latch chip-address latch sub-address latches memory & sub-address decoding acknowledge data clock clock counter reset start-bit recognition 5 8-bit 8-bit 8-bit
mc44002 MC44007 15 motorola analog ic device data a d bits 6,7 bits 6,7 bits 6,7 bits 6,7 bits 6,7 i-88 i-87 i-7a i-79 i-78 figure 7. mc44002/7 memory map data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 msb lsb a d a d a d a d memory sub-address 77 digital register, bits 0-7 memory sub-address 78 analog register, bits 0-5 memory sub-address 79 analog register, bits 0-5 memory sub-address 7a analog register, bits 0-5 memory sub-address 87 analog register, bits 0-5 memory sub-address 88 analog register, bits 0-5 memory figure 7 shows a diagram of the mc44002/7 memory map. it has 18 bytes of memory which are located at hex sub-addresses 77 to 88. sub-address 77 is used to set up the vertical timebase mode of the ic and for s-vhs switching, and consists of 8 separate data bits. the remaining 17 bytes use the least significant 6-bits as an analog control register. the contents of each are d/a converted, providing an analog control current which is distributed to the appropriate part of the circuit. bits 6 and 7 are used singularly for switching control functions. chroma decoder the main function of this section is to decode the incoming composite video, which may be in any of the pal, ntsc or secam (mc44002 only) standards, and to retrieve the luminance and color difference signals. in addition, the signal filtering and luma delay line functions are carried out in this section by means of sampled data filters. the entire decoder section operates in sampled data mode using clocks generated by external crystals. the oscillator, which is phase-locked in the usual way for pal/ntsc modes, provides the clock function for the whole circuit. the crystals are selected by the mcu by means of a control bit (xs). only crystals appropriate to the standards which are going to be received need to be fitted. a 17.7 mhz crystal (4x pal subcarrier) is used for pal and secam systems (50 hz, 625 lines); and 14.3 mhz (4x ntsc subcarrier) for the ntsc system (60 hz, 525 lines). nearly all the filters, together with the luma delay line and peaking, have been integrated, requiring no external components or any adjustment. the filter characteristics are entirely determined by the clocks and by capacitor ratios, and are thus completely independent of variations in the manufacturing process. the pal/ntsc subcarrier pll and acc loop filters have not been integrated in order to facilitate testing. these filters consist of fixed external components. figure 8 is a block diagram of the main features of the chroma decoder. selection is first made between the video 1 and video 2 inputs. these may be either normal composite video or separate luma and chroma which may enter the ic at either pin. commands from the mcu are used to route the signals through the appropriate delay and filter sections. in pal/ntsc, a variable low pass filter, which can be software bypassed (control bit t3), is then used to compensate for if filtering and the q of the external sound traps. filter response is controlled by means of control bits t1 and t2. it is not recommended to use this filter in secam or in svhs, as lumachroma delays will not be optimized. next, the video enters the luma path. the pal/ntsc or secam chroma signals are separated out by transversal high pass filters. in secam mode, the chroma trap frequency is dynamically steered to follow the instantaneous frequency of the chroma. then, another transversal filter provides luma peaking, which is also active in svhs mode. the high frequency luma may be peaked (at about 3.0 mhz with the 17.7 mhz crystal, and 2.4 mhz with the 14.3 mhz crystal) in 7 steps up to a maximum of 8.5 db, by a control word from the mcu. another control word is used to trim the delay in the luma channel. five steps of 56 ns (70 ns with the 14.3 mhz crystal) are possible, giving a total programmable delay of 280 ns. steps 6 and 7 are used in svhs mode. the resulting processed luma signal then proceeds to the color difference section after being lowpass filtered by an active filter to remove components of the crystal frequency, and twice that frequency. the luma component (y1) is made available at pin 29 for use with auxiliary external functions, as well as testing. when in the svhs mode, the svhs control bit controls the signal paths. the luma signal bypasses the first section of the luma channel, which contains the chroma trap. the svhs chroma is passed directly to the pal/ntsc decoder without further filtering. as all the delay and filter responses are determined by the crystal, they automatically commute to the new standard when the crystal is changed over. thus, when the 14.3 mhz clock is being used, the chroma trap moves to 3.58 mhz. the filtered pal/ntsc and secam chroma signals are decoded by their respective circuits. the pal/ntsc decoder employs a conventional design, using acc action for gain control and the common double balanced multipliers to retrieve the color difference signals. the secam decoder is discussed in a separate subsection.
mc44002 MC44007 16 motorola analog ic device data pal/ntsc (mcu) 29 36 37 39 1 b-y r-y secam decoder 32 33 oscillator 14.3mhz 17.7mhz c c pll acc pal/ntsc decoder 4.4/8.8mhz r-y system select hue controls v u ident (mcu) b-y 4.4/8.8mhz luma luma delay line ident data (mcu) lumachroma filters t1, t2 video 2 video 1 38 figure 8. chroma decoder agc q s-vhs crystal select s-vhs delay adj to color difference stage 11 secam cal loop 2 40 peaking syn sep t3 input select y1 notes: secam decoding available in the mc44002 only. the actual decision as to a signal's identity is made by the mcu based on data provided by 3 flags returned to it, namely: acc active, pal identified, and secam identified. control bits ssassd must be sent to set the decoder to the correct standard. this allows a maximum of flexibility, since the software may be written to accommodate many different sets of circumstances. for example, channel information could be taken into account if certain channels always carry signals in the same standard. alternatively, if one standard is never going to be received, the software can be adapted to this circumstance. if none of the flags are on, color killing can be implemented by the mcu. this occurs if the net ident signal is too low, or if the acc circuit is inactive due to too low a signal level. the demodulated color difference signals now enter the hue control section, where selection is made between pal/ntsc and secam outputs. the hue control is simply realized by altering the amplitudes of both color difference signals together. hue control is only a requirement in ntsc mode and would not normally be used for other standards. the function is usually carried out prior to demodulation of the chroma by shifting the phase of the subcarrier reference, causing decoding to take place along different axes. in the mc44002/7, hue control is performed on the already demodulated color difference signals. a proportion of the r-y signal is added or subtracted to the b-y signal and vice-versa. this has the same effect as altering the reference phase. if desired, the mc44002/7 can apply the hue control to simple pal signals. after manipulation by the saturation and hue controls, the color difference signals are finally filtered to reduce any remaining subcarrier and multiplier products. before leaving the chip at pins 36 and 37, the signals are blanked during line and frame intervals. the 64 m s chroma delay line is carried out by a companion device, the mc44140. secam decoder (mc44002 only) the secam signal from the high-pass filter enters tightly controlled agc amplifiers wrapped around a cloche filter which is a sampled recursive type, with the agc derived from a signal squarer. next, the signal is blanked during the calibration gate period and a reference 4.43 mhz is inserted during this time. the secam signal is then passed through a limiter. the frequency demodulator function is carried out by a frequency-locked-loop (f.l.l.). this consists of three components: a tracking filter, a phase detector and a loop filter. the center frequency of the tracking filter depends on three factors: internal r-c product, adjust voltage, and tuning voltage. the tracking filter is dynamically tuned by the tuning feedback from the loop-filter forming the f.l.l. the adjust control calibrates the f.l.l. and compensates for variations in the r-c product. after the f.l.l., the color difference signals are passed to another block where several functions are carried out. the signals are de-emphasized and outputs are provided to the ident section. another function of this section is to generate the i comp signal used for calibrating the f.l.l. this signal is blanked during the h-ig period to ensure that (r-y) and (b-y) output signals have a clean dc level for clamping purposes. in addition, components are added to compensate for the r-c product, and tuning offsets are introduced during the active lines for f0r/f0b. calibration of the f.l.l. takes place during every field blanking interval, starting from field retrace and ending just before the secam vertical ident sequence (bottles). the calibration current i cal is derived from i comp during the
mc44002 MC44007 17 motorola analog ic device data calibration gate (cal) and integrated by an external capacitor on pin 11. the resulting voltage v ext is then transformed to generate the adjust control voltage removing from the loop range most of the variations due to internal rc products and temperature. color difference stages this stage accepts luminance and color difference signals, together with external r,g,b and fast commutation inputs and carries out various functions on them, including clamping, blanking, switching and matrixing. the outputs, consisting of processed r,g,b signals, are then passed to the auto gray scale section. a block diagram of this stage is shown in figure 10. the y2, r-y, b-y together with r, g and b are all external inputs to the chip. the y1 signal comes from the decoder section. each of the signals is back-porch clamped and then blanked. the y2 and r,g,b inputs have their own simple sync separators, the output from which may be used as the primary synchronization for the chip by means of commands from the mcu. the fast commutation is an active high input used to drive a high speed switch; for switching between the y and color difference inputs and the r,g,b (text) inputs. after blanking, the y1 and y2 channels go to the luma selector which is controlled by means of 2 bits from the mcu. from here the selected luma signal goes to the rgb matrix. the two color difference signals pass through the saturation control. from here they go to a matrix in which g-y is generated from the r-y and b-y, and lastly, to another matrix where y is added to the three color difference signals to derive r,g,b. control bits (via the i 2 c bus) allow the matrix coefficients to be adjusted in order to suit different requirements, particularly in ntsc. table 1 shows the theoretical demodulation angles and amplitudes and the corresponding matrix coefficient values for each of the 4 selectable modes. (the a mode corresponds to the standard pal/secam/ntsc mode). although primarily intended for ntsc, this feature can also act on pal/secam or external rgb signals. the r,g,b inputs may take one of two different paths. they may either go straight to the output without further processing, or via a separate matrix and the saturation control. the path taken is controlled in software. when the latter route is selected, the r,g,b signals undergo a matrix operation to derive y. from this, r-y and b-y are easily derived by subtraction from r and b; the derived color difference signals are then subjected to saturation control. this extra circuitry allows another feature to be added to the tv set, namely the ability to adjust the color saturation of the rgb inputs. after the saturation control the derived signals are processed as before. table 1. matrix modes coefficients a b c c rr 1.0 1.577 1.539 1.556 rb 0 0.156 0.248 0.251 gr 0.513 0.443 0.462 0.504 gb 0.187 0.168 0.150 0.125 bb 1.0 1.0 1.0 1.0 br 0 0 0 0 rm 0.562 0.9 0.9 0.91 gm 0.344 0.3 0.3 0.31 ra 90 100 106 106 ga 237 236 240 246 note: bb = gain of (b out /(by) in ) = 1 (reference). br = gain of (b out /(ry) in ) = 0 (theoretically). figure 9. secam decoder (mc44002 only) secam i/p v a1 adjust rc-t compensation ident out de-emphasis tuning offsets output interface phig i rc fbk i comp cal 11 secam cal loop i cal agc a1 a2 cal x 2 squarer timing signals secam out (r-y/b-y sequen.) fll demodulator phase detector fll tracking filter loop filter cloche filter h h clamp calibration switch adjust 4.43mhz limiter v tun
mc44002 MC44007 18 motorola analog ic device data clamp clamp clamp blanking 26 25 y1 sync separator clamp y1, y2 select luma selector gate outputs 19 18 17 gate gate r-y gen b-y gen r g b y matrix blanking/fast commutation logic blanking burst gate bypass yx en blanking sync separator clamp clamp clamp 22 23 24 21 fast commutation y2 y1 saturation control figure 10. color difference stages matrix 28 inputs 27 b g r f/c b g r b-y y2 r-y y1 clamp analog contrast 10 bcl inputs
mc44002 MC44007 19 motorola analog ic device data in order to implement automatic beam current limiting (bcl), the possibility of fast contrast reduction has been added. for normal operation, the contrast control is achieved by auto grey scale output loops and is i 2 c bus controlled (see section 4). in the case of excess beam current, this control is not fast enough to protect the tube and power supply stages. it is now possible, by acting on the pin 10 voltage, to reduce the contrast about 12 db by reducing the luma gain and saturation. in the case of direct rgb mode, the rgb gains are also reduced. figure 11. typical contrast reduction pin 10 voltage (v) 0 1.0 2.0 3.0 4.0 5.0 1.0 1.0 3.0 5.0 7.0 9.0 11 13 relative contrast level (db) figure 11 is showing the typical analog contrast reduction possible as a function of the voltage on pin 10. two solutions are possible for obtaining the bcl function: 1st solution: a measure of the average and/or peak beam current is applied to pin 10, which causes a reduction of the rgb drive levels to the high voltage video amplifiers. in this case, no software control is required, but variations in color balance and saturation may be observed. a typical application is shown in figure 12. 2nd solution: the beam current flags are read and acted on by the mcu, which reduces the i 2 c bus contrast control to maintain the average beam current below the desired level. in the case of rapid and extreme beam current changes (black to white picture at high contrast level), the circuit of figure 12 may be used as a fast aging protection while the mcu is reducing the contrast through i 2 c bus. the average of this method is to make any color balance/saturation variation only transient. figure 12. automatic beam current limiter application 470 n 270 k r8 r9 1.0 m r4 10 k r1 c2 c3 12 v 2.2 m c5 c1 10 n eht r3 33 k 10 n 4.7 m d1 1n4148 910 auto gray scale control loops this section supplies current drives to the rgb cathode amplifiers and receives a signal feedback from them, proportional to the combined cathode currents. the current feedback is used to establish a set of feedback loops to control the dc level of the cathode voltage (cutoff), and gain of the signal at the cathode (white balance). there are three loops to control the dark currents dark loops and another three to control the gains bright loops. the system uses 3 lines at the end of the vertical suppression period and just before the beginning of the picture for sampling the cathode current (i.e., one line for red, one for green and one for blue). the first half of reach line is used for adjusting the gain of the channel and is usually called the abrighto adjustment period. the second half of the line is used for adjusting the dc level of the channel and is called the adarko adjustment. the theoretical circuit diagram for one channel is shown in figure 13 along with the basic equations. the dc level (ldc) and gain (g) are both controlled by 7 bit dacs which receive data directly from latches in which the required values are stored between sampling periods. figure 13. bright/dark current control brightness (b) i cont pins 17, 18 or 19 bright dark bright dark i pict gain (g) output buffer (a) i o i dc picture output current: i o(pict) = a x [ i dc = g x ((b x i cont ) + i pict )] dark sample output current: i o(dk) = a x i dc bright sample output current: i o(br) = i o(dk) a x g x i cont black level output current: i o(bk) = i o(dk) b x a x g x i cont black level output current: i o(bk) = i o(dk) x b x [i o(dk) i o(br) ] a block diagram of the complete system is illustrated in figure 16. data words from the mcu which represent the rgb color temperatures selected at the factory, are stored in latches 1,2,3 and d/a converted by dac1,2,3 to reference currents. during the bright adjustment period, a reference current pulse, whose amplitude depends on the contrast setting, is output to the cathode of the tube. the gain control is adjusted to bring the feedback current to the same value as the bright reference current, which is defined by the color intensity setting of the output considered. the currents must match each other. if not, a current will flow in resistor r producing an error voltage. this is then buffered into comparators comp1, 2 and is compared with voltage references v ref1 and v ref2 . if the error voltage is greater than v ref1 , comp1 causes the counter to count up. if the error voltage is less than v ref2 , comp2 sends a count-down command. in this way, a adeadbando is set up to prevent the outputs from continuously changing. with the color intensity dac set to about 32 d , the bright cathode current is 100 m a (10 times the dark current). during load the contents of the counter are loaded into latch 6 (for red dc) and then d/a converted. the resulting dc current is then applied as an offset to the red output amplifier, completing the loop. during the dark adjustment period, the same intensity data is used but divided by a common factor (typically 10). a black level reference pulse is applied and the feedback loop adjusts the dc levels of the cathode to obtain a set of cathode currents equal to the dark reference currents
mc44002 MC44007 20 motorola analog ic device data (10 m a). therefore, the image color will always be adjusted to match the dark level color, i.e. grey scale tracking is ensured. the load/backload sequencer is used to control which latch is being addressed at any given time by means of the timing signals input to it. the backload command sends the data from the appropriate latch to the up/down counter, ready to be modified if necessary. the brightness control is affected by simply changing the dc pedestal of all three drives by the same amount, and does not form part of the feedback loop. the contrast is adjusted to a set of values dependent on the level of the bright pulse applied during the setup period. this level is set by a control word from the mcu. once the loops have stabilized under normal working conditions, they may be deactivated by means of a control bit from the mcu. when, however, any change is made to either contrast or rgb intensity, the loops must be reactivated. for normal operation, it is not necessary to deactivate the bright loops. increasing the rgb intensity values will cause the blacktowhite cathode voltage amplitude to increase for a given contrast setting. the white balance can therefore be set by adjusting the relative values of r, g and b intensity. an extra loop has been included via latch 4 and dac 4, which operates during the field flyback time to compensate for offsets within the loop. this has the effect of counteracting any input offset from the buffer/amp and will also compensate for cathode leakage should this be needed. a second output of the reference currents from the rgb dacs are used to compare with preset limits, to ensure that the loops are working within their range of control. should the limits be exceeded in either direction, flags are returned to the mcu to request that the g2 control be adjusted up or down as appropriate. once setup, the servo loops maintain the same conditions throughout the life of the tv. horizontal timebase the horizontal timebase consists of a pll which locks up to the incoming horizontal sync, and a phase detector and shifter whose purpose is to maintain the h-drive in phase with the line flyback pulse. because of on-chip component tolerances, the free-running oscillator frequency cannot be set more accurately than 40%; this range would be too much for the line output stage to cope with. for this reason the free-running frequency is calibrated periodically by other means. during startup and whenever there is a channel change, the phase detector is disconnected from the vco for 2 lines during the blanking interval. a block diagram of the line timebase is given in figure 14. the calibration loop consists of a frequency comparator driving an up/down counter. the count is d/a converted to give a dc bias which is used to correct a 1.0 mhz vco. the 1.0 mhz is divided by 64 to give line frequency and this is returned to the frequency comparator. this compares fh from the vco with a reference derived from dividing down the subcarrier frequency. any difference in frequency will result in an output from the comparator, causing the counter to count up or down; and thus closing the loop. since the horizontal oscillator is quite stable, this calibration does not need to be carried out very often. after switchon, the calibration loop need only be enabled when the timebase goes out of lock. a coincidence detector looks at the pll fh and compares it with the incoming h-sync. if they are not in lock, a flag is returned to the mcu. to allow for use with vcrs, the gain of the phase detector may be switched by means of commands from the mcu (bits hgain1 and hgain2). the gain of the phase detector is switched to the maximum value at the end of the vertical sync pulse and then reduced to the selected value after about 11 lines. this allows the horizontal timebase to rapidly compensate any horizontal phase jump (e.g. with a vcr) during the vertical blanking period, thus avoiding bending at the top of the picture. twice line frequency is output from the pll which may be divided by either 1 or 2 depending on the command of the mcu. the x2 fh will be used with feature boxes. the phase of the fh and flyback pulses are compared in a phase detector, whose output drives a phase shifter. a 6-bit control word and d/a converter are used to apply an offset to the phase detector giving a horizontal phase shift control. the presence of the horizontal flyback pulse is detected; if it is missing a warning flag is sent back to the mcu which can take appropriate action. vertical timebase the vertical timebase consists of two sections; a digital section which includes a vertical sync separator and standard recognition; and an analog section which generates a vertical ramp which may be modified under mcu control to allow for geometrical adjustments. a parabola is also generated and may be used for pin-cushion (e-w) correction and width control (see figure 15). in the digital section, the mc44002/7 uses a video sync separator which works using feedback, such that the threshold level of a comparator (slice level) is always maintained at the center of the sync pulse. sync from any of the auxiliary inputs may also be used. the composite sync is fed to a vertical sync separator, where vertical sync is derived. this consists of a comparator, up/down counter and decoder. the counter counts up when sync is high, and down when sync is low. the output of the decoder is compared with a threshold level, the threshold only being reached with a high count during the broad pulses in the field interval. when aauto countdowno is selected, the vertical timebase in fact starts off in the ainjection locko mode. this means that the timebase locks immediately to the first signal received, in exactly the same way as an old type injection locked timebase. a coincidence detector looks for counts of the right number (525 e.g.), and causes a 4 bit counter to count up. when there are 8 consecutive coincidences, the vertical countdown is engaged, and the msb of the counter is brought out to set the flag. similarly, noncoincidence, which will occur if synchronizing pulses are missing or in the wrong place, or if there is noise on the signals, causes the counter to count down. when the count goes back to zero, after 8 noncoincidences, the timebase automatically reverts to ainjection locko mode. if it is known that lock will be lost (e.g., channel change), it is possible to jump straight into injection lock mode and not have to wait for the 8 consecutive non-coincidences. in this way the new channel will be captured rapidly. once locked on to the new channel, aauto countdowno is then reselected by the mcu. under some conditions such as some vcrs in search mode, it is possible to get signals having an incorrect number of lines, meaning that the countdown flag will go off because of successive non-coincidences. in these circumstances, if aauto countdowno is selected, the timebase will automatically lock to the signal in the injection lock mode. the fact that the
mc44002 MC44007 21 motorola analog ic device data flag is effectively saying that the vertical timebase is out of lock need not be a cause for major concern, since the horizontal timebase will still be locked to the signal, and has its own flag ahorizontal out of locko. the vertical countdown and horizontal lock flags both perform an independent test for the presence of a valid signal. a logical or function can be performed on the two flags, such that if either are present then by definition a valid signal is present. the vertical oscillator has end-stops set at two line-count decodes as given below: 50 x 625 / 740 = 42.2 hz (min) 50 x 625 / 448 = 69.8 hz (max) these figures assume that the horizontal timebase is running at 15,625 hz. when the vertical timebase is in injection lock mode, the line counter reset is inhibited so that it ignores any sync pulses before a count of 448 is reached. this prevents any possible attempted synchronization in the middle of the picture. if the count reaches 740 lines, then there is an automatic reset which effectively sets the lower frequency limit. the choice of these limits is a compromise between a wide window for rapid signal capture and a narrow window for good noise immunity. it is also possible to run the timebase in 2.0 v mode as there are decodes for 100 hz (2 x 50 hz) operation with upper and lower limits in proportion. this is, of course, intended to be used in conjunction with field and frame memory stores. the similar decodes which would be necessary to allow 120 hz (2 x 60 hz) operation have not, for the present, been implemented. finally, the timebase can be forced into a count of either 625 or 525 by commands from the mcu; in this mode the input signal, if present, is ignored completely. if there is no signal present save for noise, then this feature can be used to obtain a stable raster. in the analog section, an adjustable current source is used to charge an external capacitor at pin 6 to generate a vertical ramp. the amplitude of the ramp is varied according to the current source (height), and is automatically adapted when the 525 standard is recognized by multiplying by 1.2. the linearity control is achieved by squaring the ramp and either adding or subtracting a portion of it to the main linear current. in addition, a correction current, depending on the level of anode current, is applied in the sense of oppose a change of picture height with eht (breathing). the final ramp with corrections added is then passed to a driver/amplifier and is output at pin 7. the vertical ramp can be used to drive a separate vertical deflection power circuit with local feedback control. vertical aso correction will then be made using fixed components within the feedback loop of the power op amp. the vertical position can be adjusted under mcu control this is achieved by varying the dc output level at pin 7. the vertical amplitude can be reduced to 75% of its original value (bit vdi) to make possible the display of a 16:9 picture on a 4:3 screen. the reference ramp is squared to provide a pin-cushion correction parabola, developed across an external resistor at pin 8. the parabola itself is squared, giving an independent fourth order term (corner correction) whose level can also be varied; this is then added as a further modifying term to the e-w output. this latter correction is used for obtaining good corner geometry with flat-square tubes. a variable dc current is added to the parabola to effect a width control. using a suitable power amplifier and a diode-modulator in the line output stage, the parabola may be used for e-w correction and dynamic width control. a further control is provided to shift the center point of the parabola up and down the screen (parabola tilt). all of the vertical and horizontal signals are adjustable via 6-bit words from the mcu, and stored in latches. the adjustment controls available are: vertical amplitude/linearity/breathing correction/position parabola (e-w) amplitude/horizontal amplitude/ corner correction, and parabola tilt the anode current sense at pin 9 is also used as a beam current monitor. two thresholds may be set, by the manufacturer, using external components. the first threshold sets a flag to the processor if beam current becomes excessive. the mcu could, e.g., reduce brightness and/or contrast to alleviate the condition. the second threshold sets a flag warning of an overload condition where the crt phosphor could be damaged. if such a condition were to arise, the processor would be programmed to shut down the psu. the vertical blanking lines may be selected by means of a bit from the mcu for either the 525 or 625 standard. the interlace may also be suppressed again under the control of the processor (bits ici, ifi).
mc44002 MC44007 22 motorola analog ic device data phase detector 15 flyback in drive out (mpu) flyback detector (mpu) offset phase detector phase shifter enable/start (mpu) x2 frequency (mpu) 2 or 1 2fh 14 13 12 horizontal out of lock (mpu) coincidence detector hgain2 hgain1 fh divide by 64 1.0 mhz vco dc bias i ref calkill a d up/down counter norm (mpu) frequency comparator frequency divider fh 4.43/ 3.58 mhz figure 14. horizontal timebase figure 15. vertical timebase horizontal sync hphase flyback present vertical drive dac dac dac dac vertical amplitude (mcu) vertical linearity (mcu) vertical breathing correction (mcu) vertical position (mcu) 2fh clock line counter decoder 16fh clock composite sync horizontal amplitude (mcu) vert sync separator coincidence counter and control vertical ramp vdi (mcu) reset parabola tilt (mcu) dac anode current sense 9 7 ew drive 8 6 dac dac corner correction (mcu) parabola amplitude (mcu) x 4 x 2 dac vert modes (mcu) v countdown engaged (mcu) <576 lines (mcu) x1.2 x0.75 448 525 576 625 740 overload and excess average beam current (mcu)
mc44002 MC44007 23 motorola analog ic device data figure 16. auto gray scale control loops r intensity (mcu) latch 3 latch 2 latch 1 dac3 dac2 dac1 cathode current feedback r 2.5 v comp2 comp1 buffer v ref2 v ref1 g2 down request g2 up request to mpu b dc g dc r dc down up g2 up/down request clock debounce up/down counter offset compensation timing signals output output output b dc dac b gain dac g dc dac g gain dac r dc dac r gain dac dac4 latch 10 latch 9 latch 8 latch 7 latch 6 latch 5 latch 4 dark bright load backload blue line green line red line vertical vertical clock selector x10 amplifier load/backload sequencer r signal g signal b signal 20 17 18 19 b out g out r out latch excess peak beam current (mcu) epbc reset (mcu) g intensity (mcu) b intensity (mcu) pin function and external circuit requirements the following section describes the purpose and function of each of the 40 pins on the mc44002/7. there is also an explanation of the external circuit component requirements for a practical application; a diagram of the small signal circuit will be found in figure 17. one of the primary design aims for the mc44002/7 was to use the minimum number of external components, and where these are necessary, to employ low cost and easily obtainable standard types. thus for example, as all the video signal filtering is carried out on the ic, there are no coils required whatsoever. the most common requirement is for ac coupling capacitors which are far too big to be integrated onto the chip. the time constants on certain pins are deliberately determined by external components to facilitate testing and for fine tuning the performance.
mc44002 MC44007 24 motorola analog ic device data pin function description pin equivalent internal circuit description 1 0.1 v cc gnd acc external filter used by acc section. a single capacitor, that does not have a critical value, typically 0.01 m f, filters the feedback loop of the chroma automatic gain control amplifier. 2 40 100 nf gnd 1.0 k 20 k 20 k 14 k video input 1 (pin 40) and 2 (pin 2) video inputs (pin 2 = video 2; pin 40 = video1); intended for a nominal 1.0 vpp input level of composite video. separate luma and chroma components may also be used with these input pins for svhs. the external circuit requirement is for a coupling capacitor of 0.01 m f and a series resistance not exceeding 1.0 k w . the input selection and adaptation for y and c is carried out in software. 3 set i ref v cc gnd 8.0 k 20 k v supply 0.01 2.2 m f reference current master reference current used throughout the ic. this is programmed by means of an external pullup resistor, as onboard resistors are not sufficiently accurate. the designated current is 70 m a. this pin should be very well decoupled to ground to avoid picking up interference from the nearby i 2 c bus inputs. nominal voltage at the pin is 1.3 v. 4 gnd to mcu 150 k 70 k i 2 c clock i 2 c bus clock input. this input can be taken straight into the ic, but in a real tv application it may be prudent to fit a series current limiting resistor near the pin in case of flashover. a single pullup resistor to 5.0 v is required. although its value is associated with the m p, taking into account system capacitance at high data rates, a value of 4.7 k w , giving optimal performance, is recommended. 5 gnd to mcu 180 k 70 k i 2 c data i 2 c data input. comments above for pin 4 also apply to this pin. 6 0.082 m f v cc gnd vertical ramp a current is used to charge an external capacitor connected to this pin, developing a voltage sawtooth with a field period. the capacitor value determines the ramp amplitude. 82 nf is the more convenient value for symmetrical, linearity and parabola tilt adjustments.
mc44002 MC44007 25 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 7 v cc gnd to vertical deflection amplifier 300 m a vertical drive the sawtooth derived on pin 6 is used to drive an external power amplifier vertical output stage. the amplitude, linearity and position of the output ramp are adjustable via the mcu. 8 gnd to ew amplifier 500 parabola (ew) drive an inverted parabolic waveform derived by squaring the vertical ramp is used to drive an external power amplifier. in sets fitted with a diode modulator type line output stage, this provides width control and pincushion correction. the parabola is squared again to give a fourth order correction term required for flat square tubes. the ew amplitude, dc level, tilt and corner correction are all adjustable by means of the mcu. this is a current output and may be used, for example, to drive the virtual ground of an external power amplifier 9 gnd anode current 50 k 560 k anode current used as an anode current monitor whose purpose is to: (1) provide e.h.t. compensation (antibreathing) for the vertical ramp; and (2) provide warning of excessive and overload beam current conditions. the pin is connected via about 560 k w series resistor to the bottom of the e.h.t. overwinding. therefore, increasing beam current will pull the voltage on this pin more negative. this change is sensed within the chip and used to apply a correction to the ramp and parabola amplitudes. with large beam currents, thresholds at +v be and 2.0 v be set off warning flags to the mcu, which then has to take the appropriate action. the anode current levels at which these thresholds are reached are set up using fixed external resistors. 10 v cc gnd analog contrast 2.0 k v cc anode contrast this pin is used as an analog contrast monitor, allowing fast beam current limiting (bcl). the fast bcl is controlled by pin 10 voltage, which decreases with the contrast reduction (see typical curve). above 2.5 v on the pin, the contrast remains maximum. below 2.5, the contrast is reduced by about 12 db, which is reached at about 1.0 v. 11 100 nf gnd 200 k 200 k 10 k gnd 10 k 10 k v cc secam calibration loop this pin is used for the storage capacitor of the analog secam calibration loop (typically 100 nf). the capacitor is required regardless of whether or not secam will be decoded. 12 v cc 18 k 1.0 k 47 k 0.0047 to line o/p driver stage 5.0 v horizontal drive output horizontal drive pulses having an approximately even marktospace ratio emerge from this pin. this is an opencollector output which can sink up to 10 ma. however, taking this much current is not recommended since there is no separate ground pin available which may be connected near the line output stage; noise could be injected into the signal ground on the ic. therefore, with a transformer driven line output stage, this output has been designed to be used with an extra external transistor inverter between the ic and the line driver. the transistor is open during the period when the line deflection transistor should be conducting.
mc44002 MC44007 26 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 13 v cc gnd 50 k 120 k line flyback pulse 180 k horizontal flyback input flyback sensing input taken from the line output transformer. these pulses are used by the 2nd horizontal loop for hphase control. a positive going pulse from 0 to 5.0 v amplitude is needed for correct operation. the internal impedance of the pin is about 50 k w and an external attenuating series resistor of around 120 k w will also be needed. 14 0.1 v cc gnd horizontal loop 2 filter components at this pin filter the output of the phase detector in the 2nd horizontal loop. a simple external filter consisting of a 0.1 m f capacitor is required. 15 v cc gnd 100 k 470 pf 0.1 horizontal loop 1 filter horizontal pll loop time constant. components at this pin filter the output of the phase detector is in the 1st horizontal loop. the value of rc time constant is selected with external components to give a smooth recovery after the field interval disturbance and to ensure optimum performances in the presence of noise. 17 18 19 gnd to r, g, b amplifiers v cc 100 rgb outputs the r, g and b drives are current rather than voltage due to the limited headroom available with the 5.0 v supply line. the outputs themselves consist of opencollector transistors and these are used to drive the virtual ground point of the high voltage cathode amplifiers 20 5.0 v 220 390 feedback gnd v cc feedback current feedback sense derived from the video output amplifiers. the currents from all three guns are summed together as each is driven sequentially with know current pulses during the field interval. this feedback is then compared with internally setup references. a low value ceramic capacitor to ground may be fitted close to this pin to help stabilize the control loops. a secondary function of this pin is for peak beam current limiting. when the feedback voltage during picture time becomes too great (i.e. too high beam current), a threshold at v cc + 3.0 v be is exceeded at which time a flag is sent to the mcu. the mcu then has to carry out the function of peak beam limiter by e.g. reducing contrast until the flag goes off. the threshold current is set externally with a fixed resistor value. 21 gnd fastcommutate input v cc fast commutate a very fast active high switch (transition time 10 ns) used with text on the rgb inputs, for overlaying text on picture. this hardware switch may be enabled and disabled in software.
mc44002 MC44007 27 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 22 23 24 v cc 0.1 m f v ref rgb inputs these external input signals to the color difference stages are ac coupled into the ic via 0.1 m f capacitors. they have a clamp and sync separator. the inputs should be driven from a source of less than 1.0 k w output impedance with 700 mvpp signal levels. 25 gnd 0 . 1 m f 100 k y2 input auxiliary external input to mc44002/7 which can be used in conjunction with auxiliary color difference inputs and/or as a sync input. the pin should be driven from a source of less than 1.0 k w output impedance with 700 mvpp luminance signal. the signal must be ac coupled via an external 0.1 m f coupling capacitor. internal clamp and sync separator are provided. 26 27 v cc gnd 0.1 m f v ref 100 k by and ry inputs corrected color difference inputs from the mc44140. the signals are ac coupled via 0.1 m f capacitors and are clamped internally. the inputs should be driven from a source of less than 1.0 k w output impedance. 28 v cc gnd 4.7 m f yi clamp external capacitor used by the circuit which clamps the y1 signal output on pin 29. a typical value is 4.7 m f. 29 gnd v cc yi output the luminance, after passing through the filter and delay line/peaking sections, is made available on this pin. it is also routed internally to the color difference stages. 30 gnd v cc to mc44140 30 k system select a multilevel dc output controlled in software, which is used by the mc44140 for system selection. please refer to separate functional description of the mc44140 chroma delay line. 31 gnd v cc to mc44140 200 m a sandcastle a special multilevel timing pulse derived in the mc44002/7 for use by the mc44140. please refer to separate function description of the mc44140 chroma delay line.
mc44002 MC44007 28 motorola analog ic device data pin function description (continued) pin description equivalent internal circuit 32 33 gnd v cc to pin 1 mc44140 400 14.3 mhz 17.7 mhz 22 p 22 p 120 p 32 33 20 m a crystals (respectively 14.3 mhz and 17.7 mhz) drive for externally fitted crystal clock reference for pal, secam or ntsc. four times f sc is used. if the ntsc system is not going to be received, the 14.3 mhz crystal may be omitted. the crystal is parallel driven from a single pin and it requires a series load capacitance of appropriate value (usually 20 to 30 pf). only crystals intended for vco use should be fitted. the reference frequency is divided down in a capacitor chain to provide about 50 mv of clock reference for the mc44140. positions for pins 32 and 33 are selected by software. 34 35 5.0 v supply (35) and ground (34) supply line, nominally 5.0 v, requiring about 120 ma. the actual voltage should be in the range of 4.75 to 5.25 v for usable results. it is recommended to decouple the supply line using a small ceramic capacitor mounted close to the supply and ground pins. 36 37 v cc gnd 1.0 m 100 n to mc44140 by and ry outputs demodulated color difference outputs. these signals are ac coupled to the mc44140 for correction and delay with pal and secam respectively. signal level of about 1.4 vpp may be expected on by output when using a standard 75% color bars input video signal. 38 v cc gnd 0.047 3.0 k identification external filter used by ry identification circuit. the filter normally consists of a single capacitor whose value is a compromise between rapid identification and noise rejection. experience has shown that 0.047 m f is a suitable value. 39 v cc gnd 0.047 50 k 50 k oscillator loop filter external time constant for chroma pll. the crystal reference oscillator is phase locked to the incoming burst in pal and ntsc. a low value ceramic capacitor, for good noise immunity, is normally placed in parallel with a much longer rc time constant. the pll pullin range is reduced when the time constant on the pin is made bigger, allowing this function to be optimized by the user.
mc44002 MC44007 29 motorola analog ic device data figure 17. typical application circuit mc44002/7 1.0 k 1.0 k 0.1 0.1 5.0 v video 2 video 1 5.0 v gnd 0.1 5.0 v 0.1 47 k 0.0039 0.047 22 p 120 p 5.0 v mc44140 390 100 k 0.1 470 p 560 k 4.7 k hflyback gnd r g b f/b f/c b g r y2 ry by ry by y1 0.01 0.01 0.1 0.1 0.1 0.1 0.1 0.1 y1 out 14.3 mhz 22 p 0.047 17.7 mhz 100 n 0.01 5.0 v 0.082 0.1 120 k .0047 18 k 1.0 k hdrive 5.0 v analog anode vertical w drive data clk 0.1 0.01 47 0.022 1 2 3 4 5 6 7 8 0.1 16 15 14 13 12 11 10 9 140 239 338 437 536 635 734 833 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 5.0 v bc 337 0.1 m 2.2 f set i ref 220 m 22 m 4.7 m 22 m 1.0 5.0 v 68 m 22 m 1.0 75 75 75 75 k ry by (outputs) (inputs) (outputs) drive current contrast ry by system select sandcastle 0.01
mc44002 MC44007 30 motorola analog ic device data software control functions general description as already related in the circuit description, the mc44002/7 has a memory of 18 bytes. all, except sub-address 77 and 7f, use the 6 least significant bits as an analog control register with d/a converters (64 steps) within the memory section. the remaining bits are controlled individually for switching numerous functions. table 2 gives a listing of all the memory registers and control bits. an explanation of the function of the 16 dacs is given below. vertical amplitude changes the amplitude of the vertical ramp available on pin 7. vertical breathing correction a correction is applied to the vertical ramp amplitude in a sense opposite to the picture expansion and contraction produced by changes in beam current. this register alters the sensitivity of the beam current sensing and hence the size of correction applied for a given change in beam current. parabola amplitude changes the amplitude of the e-w output parabola developed across an external pull-up resistor at pin 8. parabola tilt shifts the point of inflection of the e-w parabola from side to side along the time axis. also known as keystone correction . vertical linearity the vertical ramp is multiplied by itself to give a squared term, a part of which is either added or subtracted to the linear ramp as determined by this register. corner correction an independent 4th order term which is subtracted from the e-w parabola to achieve correct geometry with flat square tubes. horizontal amplitude a variable dc offset applied to the e-w output parabola on pin 8. vertical position adjust the dc level of the vertical ramp on pin 7, allowing vertical centering control. horizontal phase control applies a variable phase offset to the horizontal drive pulse at pin 15 providing for a picture centering control. b, g, r intensity these controls set up the current reference pulses used when sampling the beam current during field interval. the data is fixed by the tv manufacturer when setting up the white balance and the crt for correct gray scale tracking. (all the above registers are for use during the test and setting up procedures; the remaining 4 registers are also user controls.) contrast during bright sample time during the field interval, this control varies the level of the current pulses injected into the r,g,b channels, so altering the picture contrast. brightness a variable current pedestal which is added to the three drives during active picture time. saturation a variable gain control for the two color difference signals. hue achieved by mixing a portion of one color difference signal into the other. individually adjustable control bits these consist of bits 7 and 6 of registers 77 through 88, as well as bits 0 to 5 of register 77 and bits 0 to 3 of register 7f. some of these are used individually to control single functions requiring just on/off switching; and some are arranged into 2 or 3-bit words (e.g., luma peaking). a list of control words and truth tables for these may be found in table 3. ca1, cb1 used to change the mode of operation of the vertical timebase to either injection lock or auto countdown, or to force it into 525 or 625 lines. just prior to changing channel, the vertical timebase can be switched to injection lock mode and when a new channel is captured, the timebase is switched back to auto mode. in this way there is no delay in locking onto the new channel and hence no picture roll. if there is no valid signal being received, the display can be stabilized by forcing the timebase into 525 or 625 lines. ic1, if1 these bits are used to suppress the field interlace, which can be scanned in the nearest even or odd half line. hi , vi selects the type of secam ident when operating in this mode. either vertical ident bursts or horizontal ident can be selected individually, or ident can be taken from a combination of the two. in certain transmissions the vertical secam identification is not present (and sometimes replaced by other signals), so it is strongly recommended that only the horizontal identification be used. these bits must both be set to 1 when secam is not decoded (mc44002 and MC44007). ssa, ssb, ssc used to set the color decoder and the dc level of the system select output from the mc44002/7, pin 30. this output is used by the mc44140 delay line in turn for changing between pal, ntsc, secam and external modes of operation. in effect, the mc44140 is being controlled by the i 2 c bus via the mc44002/7.
mc44002 MC44007 31 motorola analog ic device data table 2a. register memory map hex sub-address msb data byte lsb 77 t3 s-vhs fsi bai ici ifi cbi cai 78 intsel calkill vertical amplitude 79 hi vi vertical breathing correction 7a xs ssd parabola amplitude 7b t1 t2 parabola tilt 7c ssc ssa vertical linearity 7d p1 ssb corner correction 7e p3 p2 horizontal amplitude 7f d3 d1 reserved vdi nt2 nt1 nt0 80 d en d2 vertical position 81 y2 en y1 en horizontal phase control 82 test yx en blue intensity 83 not used hgain1 green intensity 84 hgain2 norm red intensity 85 bri en 2x fh contrast 86 sse h en brightness 87 ss1 not used saturation 88 v1/v2 ss2 hue 00 dummy if h en, then starts h timebase ff dummy resets peak beam limit flag
mc44002 MC44007 32 motorola analog ic device data table 2b. register memory map x x 1 1 0 1 0 ss2 1 1 0 0 ss1 sse 0 0 0 0 comp. video not used y2 rgb none sync source x x 1 1 0 1 0 ssb 1 1 0 0 ssa ssc 0 0 0 0 external none ntsc pal secam decoder enable h-drive enable luma from decoder double fh select 625/50hz phase detector gain reduction by 3 enable luma matrix luma delay in multiples of 56 ns or 70 ns force pal mode select in delay line select video input enable abrighto sample phase detector gain redution by 2 for production test enable y2 input disable rgb input luma peaking xtal select reduce vertical time constant calkill vi ssd t2 ssa ssb p2 d1 d2 y1 en yx en hgain1 norm 2x fh h en not used ss2 intsel hi xs t1 ssc p1 p3 d3 d en y2 en test not used hgain2 bri en sse ss1 v1/v2 lp4 1 1 lp3 0 1 1 0 0 0 t2 t1 lp2 lp1 lpf response none 1 1 v only 0 1 1 0 0 0 vi hi h only h + v secam ident vertical blanking (0 = for 525 lines, 1 = for 625 lines) cai cbi ifi ici bai fsi svhs t3 auto count. 1 inject. lock 0 1 0 cbi force 525 force 625 sync mode odd 1/2 line 1 1 0 1 x 0 ifi ici even 1/2 line interlaced field scan cai 0 1 1 0 disable calibration loop nt0 nt1 nt2 vdi a 0 b 1 0 1 nt2 d c matrix mode ssa 1 x 1 1 50 hz/100 hz field rate (0 50 hz; 1 = 100 hz comp video/svhs switching (0 = svhs; 1 = composite variable low pass filter (0 bypassed; 1 = enabled) 77 vertical display mode; (0 = 16:9; 1 = 4:3) reserved d3 7f d1 0 0 1 1 nt1 x x x x nt0 b 1 d 0 1 x c a 0 x x x 0 1 1 x 0 0 0 1 notes: secam decoding is selectable in the mc44002 only. hi and v i must be set to 1,1 in nonsecam applications.
mc44002 MC44007 33 motorola analog ic device data table 3. control bit truth tables cai cbi sync mode ici ifi field scan 0 0 force 625 0 x interlaced 0 1 force 525 1 0 even up 1/2 line 1 0 injection lock 1 1 odd up 1/2 line 1 1 auto countdown hi vi secam ident t1 t2 lpf response 0 0 h + v 0 0 lp1 0 1 h only 0 1 lp2 1 0 v only 1 0 lp3 1 1 none 1 1 lp4 ssc ssa ssb color diff. source sse ss1 ss2 sync source 0 0 0 secam 0 0 0 none 0 0 1 pal 0 0 1 rgb 0 1 0 ntsc 0 1 0 y2 0 1 1 none 0 1 1 not used 1 x x external 1 x x comp. video p2 p1 p3 luma peak (db) @ 3.0 mhz * ssa nt2 nt1 nt0 matrix mode 0 0 0 8.5 0 0 0 x a 0 0 1 8.0 0 0 1 0 d 0 1 0 7.2 0 0 1 1 a 0 1 1 6.3 0 1 0 0 b 1 0 0 5.4 0 1 0 1 a 1 0 1 3.8 0 1 1 0 c 1 1 0 2.3 0 1 1 1 a 1 1 1 0.0 1 0 0 x a *v l h f 177mh t l 1 0 1 x d * value shown for 17.7 mhz crystal. peak frequency is 2.2 mhz when using 14.3 mhz crystal. 1 1 0 x b peak frequency is 2 . 2 mhz when using 14 . 3 mhz crystal . 1 1 1 x c hgain1 hgain2 hphase detector gain 0 0 divide by 3 (sync window enabled) 0 1 divide by 6 (sync window enabled) 1 0 high (sync window disabled) 1 1 divide by 2 (sync window disabled) d1 d2 d3 pal (t3 = 1) ntsc (t3 = 1) secam (t3 = 0) svhs (t3 = 0) 0 0 0 780 ns 940 ns 1050 ns n/a 0 0 1 836 ns 1010 ns 1106 ns n/a 0 1 0 892 ns 1080 ns 1162 ns n/a 0 1 1 948 ns 1150 ns 1218 ns n/a 1 0 0 1004 ns 1220 ns 1274 ns n/a 1 0 1 1060 ns 1290 ns 1330 ns n/a 1 1 0 n/a n/a n/a 480 ns 1 1 1 n/a n/a n/a 480 ns
mc44002 MC44007 34 motorola analog ic device data sse, ss1, ss2 these 3 bits select the signal input from which the timebase synchronization is taken. the composite video input has a high quality sync separator which has been designed to cope with noise and interference on the video; the rgb and y2 inputs have simple single sync separators which may also be used for synchronization. t1, t2 the bits are used to modify the response of the variable low pass filter placed at the composite video inputs (for pal/ntsc signals) in order to compensate for if filtering and the q of external sound traps. p1, p2, p3 these 3 bits are used to adjust the luma peaking value. the amount of peaking indicated is with respect to the gain at the minimum peaking value (p1, p2, p3 = 111). d1, d2, d3 these 3 bits are used to adjust the luma delay. the indicated delay is that from the video inputs (pins 2 and 40) to the y1 output. the amount of delay depends on the composite video standard used if svhs is selected. nt0, nt1, nt2 these 3 bits are used in conjunction with ssa for the selection of the matrix coefficients mode. hgain1 , hgain2 these 2 bits are used to set the gain of the horizontal phase detector. the high gain position is used to acquire lock and for operation with a vcr. setting hgain1 to 0 also enables a horizontal sync window. the low gain position is used for offtheair signals. the remaining control bits are used singularly and are listed as follows: t3 when high, this bit enables the variable low pass filter at the video inputs. for optimum performance, t3 must be set to 0 in svhs and secam modes, and to 1 in pal and ntsc. the filter response is set with bits t1, t2. s-vhs set to 1 for normal composite video input to pin 2 or 40. in this mode, the lumachroma separator is active. set to 0 for svhs (y/c) operation at those pins. in this mode, luma is to be applied to the selected video input (with bit v1/v2), and chroma is to be applied to the other input. the lumachroma separator is bypassed. fsi selects either 50 hz or 100 hz field rate. when bit is low, 50 hz operation is selected. no usable with ntsc. bai this bit selects the number of blanked lines for either 525 or 625 line standards. intsel the vertical sync separator operates by starting a counter counting up at the beginning of each sync pulse, a field pulse being recognized only if the counter counts up to a sufficiently high value. the control bit intsel is used in taking the decision as to when a vertical sync pulse has been detected. when low, the pulse is detected after 36 m s; when high after 68 m s. this may find application with anti-copy techniques used with some vcrs, which rely on a modified or corrupted field sync to allow a tv with a short time constant to display a stable picture. however, a vcr having a longer time constant will be unable to lock to the vertical. calkill enables or disables the horizontal calibration loop. the loop is normally enabled only during startup for some seconds and when there is no signal present. the loop may be disabled so long as the horizontal timebase is locked to an incoming signal. xs is used to change between the two external crystal positions (pins 32 and 33). ssd forces system select to pal level. can be used to override secam mode in the delay line. when low, secam mode is enabled (mc44002 only). vdi either 4:3 or 16:9 display mode can be chosen using this bit. when low, the 16:9 mode is enabled. d en enables or disables the rgb fast commutation switch for the rgb inputs. when low, rgb inputs are enabled. y1 en switches y1 through to the color difference stage. y2 en switches y2 through to the color difference stage. test when bit is low, enables continuous sampling by the rgb output control loops throughout the entire field period. used only for testing the ic. yx en enables the luma matrix allowing saturation control in the color difference stage. norm alters the division ratio for the reference frequency used by the horizontal calibration loop. always used when changing between 14.3 mhz and 17.7 mhz crystals. bri en used to switch on or off the abrighto sampling pulses used by the rgb output loops. this feature was originally introduced to prevent any backscatter from these three bright lines in the field interval from getting into the picture. must be enabled when adjusting intensity contrast or red, green and blue. 2x fh line drive output is either standard 15.625 khz (15.750 khz) or at double this rate. h en control bit enables horizontal drive pulse. this is normally done automatically after the values stored in the mcu nonvolatile memory have been read into the mc44002/7 memory. v1/v2 to select between video inputs 1 and 2.
mc44002 MC44007 35 motorola analog ic device data table 4. control bit functions bits bit low bit high t3 variable input lpf bypassed variable input lpf enabled svhs svhs mode enabled composite video mode enabled fsi 50 hz field rate selected 100 hz field rate selected bai vertical blanking for 525 lines vertical blanking for 625 lines intsel short vertical timeconstant long vertical timeconstant calkill h calibration loop enabled h calibration loop disabled xs 17.7 mhz crystal (pin 33) selected 14.3 mhz crystal (pin 32) selected ssd system select active system select forced to pal d en rgb inputs enabled rgb inputs disabled y2 en external luma input switched aoffo external luma input switched aono y1 en luma from filters switched aoffo luma from filters switched aono test video outputs sampled continuously video outputs sampled once per field yx en disable luma matrix (rgb saturation control) enable luma matrix (rgb saturation control) hgain1 hphase detector gain division by 3 enabled hphase detector gain division by 3 disabled hgain2 hphase detector gain division by 2 disabled hphase detector gain division by 2 enabled norm hreference divider ratio for 17.7 mhz crystal hreference divider ratio for 14.3 mhz crystal bri en abrighto sample switched aoffo abrighto sample switched aono 2 x fh hdrive : 1 x fh hdrive : 2 x fh h en hdrive enabled hdrive disabled vdi 16:9 display mode enabled 4:3 display mode enabled v1/v2 video input 2 (pin 2) selected video input 1 (pin 40) selected
mc44002 MC44007 36 motorola analog ic device data flags returned by the mc44002/7 when the address read/write bit is high the last two bytes of i 2 c data are read by the mcu as status flags; a listing of these may be found in table 5. the mc44002/7 is designed to be part of a closed-loop system with the mcu; these flags are the feedback mechanism which allow the mcu to interact with the mc44002/7. a brief description of each of the flags, its significance and possible uses are given below. table 5. flags returned clock # flag (bit high) 10 horizontal flyback present 11 horizontal drive enabled 12 horizontal out of lock 13 excess average beam current 14 less than 576 lines 15 vertical countdown engaged 16 overload average beam current 17 reserved 18 (acknowledge) 19 grid 2 voltage up request 20 grid 2 voltage down request 21 ok 22 fault 23 acc active 24 pal identified 25 secam identified (mc44002 only) 26 excess peak beam current 27 (acknowledge) horizontal flyback present a sense of the horizontal flyback is taken via a current limiting series resistor from one of the flyback transformer secondaries to pin 13. this is used for the h-phase shift control, but the presence of the pulse is also flagged to the mcu. should the flag be missing after the chassis has been started up, then the mcu would have to shut down the set immediately. horizontal drive enabled indicates that the horizontal drive pulse output at pin 15 has been enabled. this occurs after the stored values in the nonvolatile memory have been transferred to the mc44002/7 memory. horizontal out of lock this flag is high when no valid signal is being received by the mc44002/7. possible action in this case would be to change the phase detector gain and time constant bits to ensure rapid capture and locking to a new signal. excess average beam current this is one of two threshold levels which are determined by an external component network connected to the beam current sensing at pin 9. this flag indicates an excess of beam current. a typical application of this flag in conjunction with aoverload average beam currento flag is for the software controlled automatic beam current limiting. when this flag is aono, it is recommended that the software prevent increases to the contrast setting. less than 576 lines output from the line counter in the vertical timebase. if there is a count of less than 576 this is indicative of a 525 line system being received. if the flag is low then a 625 line system is being received. this information can be used as part of an automatic system selection software. vertical countdown engaged the vertical timebase is based on a countdown system. the timebase starts in injection lock mode and when vertical retrace is initiated a 4-bit counter is set to zero. a coincidence detector looks for counts of 625 lines. in auto mode each coincidence causes the counter to count up. when eight consecutive coincidences are detected, the countdown is engaged. the msb of the counter is used to set this flag to the processor. overload average beam current this is the second threshold level which is set by the external component network on pin 9. the flag warns of an overload in anode current which should be lowered by reducing the contrast. grid 2 voltage up/down requests these flags indicate when the rgb output loops are about to go out of the control range necessary for correct gray scale tracking. these 2 flags are used during factory adjustment. ok and fault these two flags are included as a check on the communication line between the mcu and mc44002/7. the ok flag is permanently wired high and fault is permanently wired low. the mcu can use these flags to verify that the data received is valid. acc active this flag is high when there is a sufficient level of burst present in pal and ntsc modes during the video back porch period. the flag goes low when the level of burst falls below a set threshold or if the signal becomes too noisy. the flag is used to implement a software color killer in pal and ntsc and is also available for system identification purposes. since in secam there is line carrier present during the gating period, it is quite likely that the acc will be on, or will flicker on and off in this mode. * pal identified recognizes the line-by-line swinging phase characteristic of the pal burst. when this flag is on together with the acc flag, this is positive identification for a pal signal. * secam identified senses the changing line-by-line reference frequencies (fo1 and fo2) present during the back porch period of the secam signal. this flag alone provides identification that secam is being received (mc44002 only). excess peak beam current a voltage threshold is set on the beam current feedback on pin 20, which is also used for the rgb output loops for current sampling. when the threshold is reached, the flag is set, indicating too high a peak beam current which may be in only a part of the screen. the response of the mcu might be to reduce the contrast of the picture. this flag, together with the excess average beam current flag, performs the function of beam limiting. the exact way in which this is handled is left to the discretion of the user who will have their own requirements, which may be incorporated by the way in which the software is written. * these two flags are set in opposition to one another such that they can never both be on at the same time. this has been done to try to prevent misidentification from occurring. often it is very difficult to distinguish between pal and secam especially when broadcast material has been transcoded, sometimes badly, leaving e.g. large amounts of secam carrier in a transcoded pal signal (also often with noise). with this method the strongest influence will win out making a misidentification much less likely.
mc44002 MC44007 37 motorola analog ic device data appendix a system identification table the table below can be used for color standard selection between the normal pal (i, bg), secam (l, bg) and ntsc (3.58 mhz m) standards. detecting the hybrid vcr standard (525 lines with 4.4 mhz chrominance) would entail switching back to the 17.7 mhz crystal in the event of there being no flag present with the 14.3 mhz crystal. the mc44002/7 could also be used for the pal m and n standards that are used in some parts of south america, but because the subcarrier frequencies differ by some khz from the normal, crystals with a different center frequency would be required. table 6. system identification flags from the mc44002/7 <576 lines acc on pal secam crystal (mhz) standard selected by mcu 0 0 0 0 17.7 kill 0 0 0 1 17.7 secam 0 0 1 0 17.7 kill 0 0 1 1 17.7 i 2 c bus error 0 1 0 0 17.7 kill 0 1 0 1 17.7 secam 0 1 1 0 17.7 pal 0 1 1 1 17.7 i 2 c bus error 1 0 0 0 14.3 ntsc kill 1 0 0 1 14.3 ntsc kill 1 0 1 0 14.3 ntsc kill 1 0 1 1 14.3 i 2 c bus error 1 1 0 0 14.3 ntsc 1 1 0 1 14.3 ntsc 1 1 1 0 14.3 ntsc 1 1 1 1 14.3 i 2 c bus error
mc44002 MC44007 38 motorola analog ic device data appendix b i 2 c bus and rgb control loops with mc44002/7 the rgb drive dacs cannot be buffered on account of the chip area that this would take up. this factor has considerable implications on the way that the i 2 c data is written into the mc44002/7 memory. if the data for brightness, contrast, saturation and hue are transmitted at just any time, a disturbance will be visible on the screen. to overcome this difficulty, a method synchronizing the mcu to write data only during the field interval has been developed. this represents something of a limitation, but has to be used only for the 4 user controls. another characteristic of the mc44002/7 is that the contrast control function is carried out within the rgb sampling loops. if data is written into the registers during the time when the rgb loops are taking their samples, then the situation arises where data is being sampled and changed at the same time. hence, the loops will inevitably go unstable. when this happens, the brightness is seen to vary uncontrollably while the contrast is changed. the effect has been described as aloop bounceo. the timing diagram below show the exact situation. from the start of the field flyback pulse to the beginning of the rgb sampling, approximately 1.2 ms is available to write the i 2 c data. therefore, with a reasonable safety margin, the write time should be limited to only about 1.0 ms. this should not present any serious difficulty since only the data byte has to be transmitted during this time, and then only for the 4 user controls. 1.2 ms loop sampling waveform (pin 20) video field interval field flyback synchronizing pulse rgb
mc44002 MC44007 39 motorola analog ic device data appendix c a suggested method for output loops adjustment as described in section 4, the mc44002/7 output loops stage automatically adjust the dc level of the cathode voltage (cutoff) and the gain of the signal at the cathode (white balance). these automatic adjustments replace the conventional manual adjustments. the only adjustment that must be carried out, either by hand or automatically using an aintelligent screwdrivero, is for the g2 voltage. as the g2 voltage is varied, the automatic output loops of the mc44002/7 will adjust the cathode voltage of the dark sample level to always obtain the correct dark cathode current. however, if the g2 voltage is adjusted too high or too low, one or more of the dac's controlling the dc level will reach the end of their range and the cathode voltage on the channel will not be correctly adjusted. in order to inform the operator or machine adjusting the g2 voltage that the control range has been exceeded, the g2up request or g2down request flags will be set. these flags are set when any one of the dcdac's approaches the end of its range. the threshold for setting the flags lies typically between 15 and 20% of the range from the actual end. therefore, when a flag is set, the output loops can still operate correctly. as the gain of the picture tube varies very little with the g2 voltage, flags are not provided for the gaindac's. in order to fix a procedure for setting the g2 voltage it is necessary to consider several points: on a given sample, the output currents from the three channels corresponding to the dark level are all different. the range of each dac is about 2.4 ma and varies little from one channel to another and from one device to another. for reasons of stability and control range we recommend that the feedback resistor of the highvoltage video amplifier be 39 k w . this means that the dark cathode voltage range of each channel is about 94 v (i.e. 39 k w x 2.4 ma), but the absolute value of the cathode voltage can vary. in a typical application the actual cutoff voltage (i.e. zero cathode current) lies about 1015 v higher than the dark cathode current (10 m a). when the beamcurrent in the picture tube increases, the g2 voltage tends to decrease. with the output loops of the mc44002/7, the cathode voltage is lowered automatically to compensate, but this effect would normally cause the values in the dcdac's to fall, using up their useful control range. as high beam current is associated to high contrast, in the mc44002/7 the dc output current (and therefore the cathode voltage) is reduced directly as the contrast setting is increased. in this way as contrast is increased, leading to higher beam current and lower g2 voltage, the dcdac's do not move much, thus saving range. a picture tube can have a difference in cutoff voltage between guns of up to about 30 v and it is not generally possible to identify in a particular type and make of tube which gun has the lowest and which gun has the highest cutoff voltage. also, it is generally recommended by the tube manufacturer to set the cutoff voltage of the highest gun to a certain value which gives optimum focus performance. as the picture tube ages, the cathode cutoff voltage falls. it is therefore best to set the g2 voltage when the tube is new to give the highest possible cathode cutoff voltage. taking into account the above points, it is recommended that the g2 voltage be set up in the following way: 1) display a black picture with the brightness control to minimum. (this give minimum beam current and no drop in g2 voltage.) 2) set he contrast to maximum. (this causes the dc output current to be forced to a lower level and the output loops to compensate by moving towards the top of their range.) 3) now adjust the g2 voltage so that the g2 down request flag is just turned off. (all the dcdac's are towards the top of their range and the highest one is just at the level to switch on the flag. lowering the contrast setting, increasing the beam current or aging of the tube will cause the output loops to reduce the values in the dcdac's, but the available range will be a maximum.) 4) with a white picture and contrast set to give the maximum allowable beam current, check that the g2 up request flag is still off. (this is just to check that the g2 voltage is not falling too much at high beam current, but this step is not absolutely necessary.) it is not recommended adjusting the g2 voltage to reach a specific value of cathode cutoff or dark voltage. the reason for this is that tolerances of the picture tube, high voltage video amplifier and the mc44002/7 itself will cause the dcdacs to be set anywhere in their range and perhaps near the bottom end, leaving no margin for aging and g2 voltage drop.
mc44002 MC44007 40 motorola analog ic device data p suffix plastic package case 71103 issue c outline dimensions notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 20 40 21 b a c seating plane d f g h k n m j l dim min max min max inches millimeters a 51.69 52.45 2.035 2.065 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc44002/d ?

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